Algorithm and VLSI Architecture for Real-Time 1080p60 Video Retargeting
In this work, we devise an efficient video retargeting algorithm by following an algorithm-architecture co-design approach and we present the first FPGA implementation that is able to retarget full HD 1080p video at up to 60 frames per second.
June 27, 2012
High Performance Graphics 2012
Authors
Pierre Greisen (Disney Research/ETH Joint PhD)
Manuel Lang (Disney Research/ETH Joint PhD)
Simon Heinzle (Disney Research)
Aljoscha Smolic (Disney Research)
Algorithm and VLSI Architecture for Real-Time 1080p60 Video Retargeting
Aspect ratio retargeting for streaming video has actively been researched in the past years. While the mobile market with its huge diversity of screen formats is one of the most promising application areas, no existing algorithm is efficient enough to be embedded in such devices. In this work, we devise an efficient video retargeting algorithm by following an algorithm-architecture co-design approach and we present the first FPGA implementation that is able to retarget full HD 1080p video at up to 60 frames per second. We furthermore show that our algorithm can be implemented on embedded processors at interactive framerates. Our hardware architecture only requires
a modest amount of hardware resources, and is portable to a dedicated ASIC for the use in consumer electronic
devices such as displays or mobile phones
